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CY62148E MoBL(R)
4-Mbit (512 K x 8) Static RAM
4-Mbit (512 K x 8) Static RAM
Features

Functional Description
The CY62148E is a high performance CMOS static RAM organized as 512 K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), Outputs are disabled (OE HIGH), or during an active Write operation (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Very high speed: 45 ns Voltage range: 4.5 V to 5.5 V Pin compatible with CY62148B Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A (Industrial) Ultra low active power Typical active current: 2.0 mA at f = 1 MHz Easy memory expansion with CE, and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Available in Pb-free 32-pin thin small outline package (TSOP) II and 32-pin small-outline integrated circuit (SOIC)[1] packages

Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE
INPUT BUFFER ROW DECODER
I/O IO00 I/O IO11
SENSE AMPS
I/O IO22 I/O IO33 I/O IO4 4 I/O IO55 I/O IO66 I/O
512K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO77
A13 A14
A15
A16
A17
Note 1. SOIC package is available only in 55 ns speed bin.
Cypress Semiconductor Corporation Document #: 38-05442 Rev. *H
*
198 Champion Court
A18
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 23, 2010
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CY62148E MoBL(R)
Contents
4-Mbit (512 K x 8) Static RAM .......................................... 1 Features ............................................................................. 1 Functional Description ..................................................... 1 Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Capacitance ...................................................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definitions ............................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14
Document #: 38-05442 Rev. *H
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CY62148E MoBL(R)
Pin Configuration
Figure 1. 32-Pin SOIC/TSOP II Pinout Top View
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
Product Portfolio
Power Dissipation VCC Range (V) Typ[2] 5.0 5.0 Operating ICC (mA) Speed (ns) Typ[2] 45 55 2 2 f = 1 MHz Max 2.5 2.5 f = fmax Typ[2] 15 15 Max 20 20 Standby ISB2 (A) Typ[2] 1 1 Max 7 7
Product CY62148ELL CY62148ELL TSOP II SOIC
Range Industrial Industrial/ Automotive-A
Min 4.5 4.5
Max 5.5 5.5
Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C.
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CY62148E MoBL(R)
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ............................... -65 C to + 150 C Ambient temperature with power applied .......................................... -55 C to + 125 C Supply voltage to ground potential.................. -0.5 V to 6.0 V (VCCmax + 0.5 V) DC voltage applied to outputs in high Z state [3, 4] .............. -0.5 V to 6.0 V (VCCmax + 0.5 V) DC input voltage [3, 4] .......... -0.5 V to 6.0 V (VCCmax + 0.5 V) Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current ......................................................>200 mA
Operating Range
Device CY62148E Range Ambient Temperature VCC[5]
Industrial/ -40 C to +85 C 4.5 V to 5.5 V Automotive-A
Electrical Characteristics
Over the operating range Parameter VOH VOL VIH VIL Description Test Conditions 45 ns Min 2.4 - 2.2 -0.5 - -1 -1 Typ[7] - - - - - - - 15 - - 2 1 Max - 0.4 VCC + 0.5 0.8 - +1 +1 20 2.5 7 Min 2.4 - 2.2 - -0.5 -1 -1 - - - 55 ns [6] Typ[7] - - - - - - - 15 2 1 Max - 0.4 VCC + 0.5 - 0.6[8] +1 +1 20 2.5 7 A A A mA Unit V V V V
Output HIGH voltage IOH = -1 mA Output LOW voltage IOL = 2.1 mA Input HIGH voltage VCC = 4.5 V to 5.5 V Input LOW voltage VCC = 4.5 V to 5.5 V For TSOPII package For SOIC package
IIX IOZ ICC ISB2 [9]
Input leakage current GND < VI < VCC Output leakage current GND < VO < VCC, output disabled VCC = VCC(max) IOUT = 0 mA CMOS levels
VCC operating supply f = fmax = 1/tRC current f = 1 MHz Automatic CE power-down current -- CMOS inputs
CE > VCC - 0.2 V VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max)
Notes 3. VIL(min) = -2.0 V for pulse durations less than 20 ns for I < 30 mA. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 6. SOIC package is available only in 55 ns speed bin. 7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This is applicable to SOIC package only. Refer to AN13470 for details. 9. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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CY62148E MoBL(R)
Capacitance
Parameter[10] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(Typ) Max 10 10 Unit pF pF
Thermal Resistance
Parameter [10] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 3.0 V GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board SOIC Package 75 10 TSOP II Package 77 13 Unit C/W C/W
Equivalent to:
THEVENIN EQUIVALENT
RTH OUTPUT Parameter [10] R1 R2 RTH VTH V
5.0 V 1800 990 639 1.77
Unit V
Data Retention Characteristics
Over the operating range Parameter VDR ICCDR[12] tCDR tR[13] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time TSOP II SOIC VCC= VDR, CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V Industrial/ Automotive-A Conditions Min 2 - 0 45 55 Typ[11] - 1 - - - Max - 7 - - - Unit V A ns ns ns
Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 12. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
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CY62148E MoBL(R)
Figure 3. Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 2.0 V
VCC(min)
tR
CE
Switching Characteristics
Over the operating range Parameter [14] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[18] Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z [16, 17] WE HIGH to low Z [16] 45 35 35 0 0 35 25 0 - 10 - - - - - - - - 18 - 55 40 40 0 0 40 25 0 - 10 - - - - - - - - 20 - ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z [16] OE HIGH to high Z [16, 17] CE LOW to low Z
[16]
45 ns Description Min Max Min
55 ns[15] Unit Max
45 - 10 - - 5 - 10 - 0 -
- 45 - 45 22 - 18 - 18
55 - 10 - - 5 - 10 - 0
- 55 - 55 25 - 20 - 20 - 55
ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to high Z [16, 17] CE LOW to power-up CE HIGH to power-down
45
-
Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 5. 15. SOIC package is available only in 55 ns speed bin. 16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 18. The internal wre.ite time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62148E MoBL(R)
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [19, 20]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [20, 21]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [22, 23]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 24 tHZOE DATA VALID tHD
Notes 19. Device is continuously selected. OE, CE = VIL. 20. WE is HIGH for read cycles. 21. Address valid before or similar to CE transition LOW. 22. Data I/O is high impedance if OE = VIH. 23. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 24. During this period, the I/Os are in output state and input signals must not be applied.
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CY62148E MoBL(R)
Figure 7. Write Cycle No. 2 (CE Controlled) [25, 26]
tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
CE
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [26]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 27 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE H[28] L L L WE X H L H OE X L X H High Z Data out Data in High Z I/O Read Write Selected, outputs disabled Mode Deselect/power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Notes 25. Data I/O is high impedance if OE = VIH. 26. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 27. During this period, the I/Os are in output state and input signals must not be applied. 28. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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CY62148E MoBL(R)
Ordering Information
Table 1 lists the CY62148E MoBL(R) key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Key features and Ordering Information Speed (ns) 45 55 Ordering Code CY62148ELL-45ZSXI CY62148ELL-45ZSXA CY62148ELL-55SXI CY62148ELL-55SXA Package Diagram Package Type Operating Range Industrial Automotive-A Industrial Automotive-A
51-85095 32-Pin TSOP II (Pb-free) 51-85095 32-Pin TSOP II (Pb-free) 51-85081 32-Pin SOIC (Pb-free) 51-85081 32-Pin SOIC (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 4 8 E LL 45/55 ZSX SX I/A Temperature grades: I = Industrial A = Automotive-A 32-Pin SOIC (Pb-free) 32-Pin TSOP II (Pb-free) Speed grade (45 ns, 55 ns) LL = Low power Process technology: 90-nm Bus Width = x8 Density = 4 Mbit Family: Low power SRAM Company ID: CY = Cypress
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Package Diagrams
Figure 9. 32-Pin TSOP II, 51-85095
51-85095-*A
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CY62148E MoBL(R)
Figure 10. 32-Pin (450-Mil) Molded SOIC, 51-85081
51-85081-*C
Acronyms
Acronym CMOS I/O MoBL SOIC SRAM VFBGA TSOP input/output more battery life small-outline integrated circuit static random access memory very fine ball grid array thin small outline package Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol ns V A mA pF C W volts micro amperes milli amperes pico Farad degree Celsius watts Unit of Measure nano seconds
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CY62148E MoBL(R)
Document History Page
Document Title: CY62148E MoBL(R) 4-Mbit (512 K x 8) Static RAM Document Number: 38-05442 Revision ** *A ECN 201580 249276 Orig. of Change AJU SYT Submission Date 01/08/04 See ECN New datasheet Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Added RTSOP II and Removed FBGA Package Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Corrected typo in Package Name Changed Ordering Information to include Pb-free Packages Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 35ns Speed Bin Removed "L" version of CY62148E Changed ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Max) value from 2 mA to 2.5 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f=fmax Removed ISB1 spec from the Electrical characteristics table Changed ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A Modified footnote #4 to include current limit Removed redundant footnote on DNU pins Changed the AC testload capacitance from 100 pF to 30 pF on page #4 Changed test load parameters R1, R2, RTH and VTH from 1838 , 994 , 645 and 1.75 V to 1800 , 990 , 639 and 1.77 V Changed ICCDR from 2.5 A to 7 A Added ICCDR typical value Changed tLZOE from 3 ns to 5 ns Changed tLZCE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 22 ns to 25 ns Updated the ordering information table and replaced Package Name column with Package Diagram Included Automotive Range in product offering Updated the Ordering Information Corrected the operating range to 4.5 V - 5.5 V on page# 3 Added footnote #8 Added VILspec for SOIC package. Description of Change
*B
414820
ZSD
See ECN
*C *D *E
464503 485639 833080
NXR VKN VKN
See ECN See ECN See ECN
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Document History Page (continued)
Document Title: CY62148E MoBL(R) 4-Mbit (512 K x 8) Static RAM Document Number: 38-05442 Revision *F ECN 890962 Orig. of Change VKN Submission Date See ECN Description of Change Added Automotive-A part and its related information Removed Automotive-E part and its related information Added footnote #2 related to SOIC package Added footnote #9 related to ISB2 Added AC values for 55 ns Industrial-SOIC range Updated Ordering Information table Added "CY62148ELL-45ZSXA" part in Ordering information. Added footnote related to chip enable in Truth Table Updated Package Diagrams Added Contents, PSoC Solutions, and Sales, Solutions, and Legal Information. Template update. Updated table of contents. Added acronyms, units of measure and ordering code definitions. Added reference to note 12 to parameter ICCDR on page 5.
*G
2947039
VKN
06/10/2010
*H
3006318
AJU
08/23/10
Document #: 38-05442 Rev. *H
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CY62148E MoBL(R)
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05442 Rev. *H
Revised August 23, 2010
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More Battery Life is a trademark and MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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